Remember bitwise operations exist for addressing

It's been a long time since undergrad -- okay?

Instructions from the MIX specification frequently use a Word for
addressing. A given Instruction's address should be the W(0:2) field
specification, note this includes the sign.

diff --git a/src/main.rs b/src/main.rs
index 0fedeee..727b3f6 100644 (file)
--- a/src/main.rs
+++ b/src/main.rs
@@ -5,14 +5,21 @@ struct MixBit {
 
 impl MixBit {
     // Clamps a u8 to a u6
+    // 0b0011_1111 = 64
     fn value(&self) -> u8 {
-        return self.v % 64;
+        return self.v & 0b0011_1111;
     }
 
     fn as_value(&self) -> MixBit {
         MixBit { v: self.value() }
     }
 }
+
+// Useful function for "packed" bits like those used for opcodes
+fn address(high: MixBit, low: MixBit) -> u16 {
+    return ((high.value() as u16) << 6) | low.value() as u16;
+}
+
 // > Each byte contains an unspecified amount of information but it must be capable of holding at
 // > least 64 distinct values.
 // > A computer word consists of five bytes and a sign. The sign portion has only two possible
@@ -64,7 +71,7 @@ struct Registers {
     rJ: Word,
 }
 
-// hacing three values: LESS, EQUAL, or GREATER
+// having three values: LESS, EQUAL, or GREATER
 #[derive(Debug, Default)]
 enum ComparisonIndicator {
     Less,
@@ -99,12 +106,10 @@ impl Machine {
 }
 
 fn main() {
-    println!(
-        "{:?}",
-        Word {
-            sign: true,
-            bytes: [MixBit { v: 255 }; 5]
-        }
-        .field_specification(0, 2)
-    );
+    let fs = (Word {
+        sign: true,
+        bytes: [MixBit { v: 255 }; 5],
+    })
+    .field_specification(0, 2);
+    println!("{:?}", address(fs.bytes[0], fs.bytes[1]));
 }