Fix a panic in as_field_spec

When field specs got implemented correctly 0 stopped representing the
"special case" where we read a word without modifications. I just need
to make note that the F byte should be 5 for now in that case. Anything
that is unrepresentable should probably _also_ represent that case, so
63 would be a fine number as well.

diff --git a/src/machine.rs b/src/machine.rs
index fdecd3307ebbdeb88c5d08cd72283a6e42d6914e..f4ae6497026683ea8b6b30b30b84119cb2227af5 100644 (file)
--- a/src/machine.rs
+++ b/src/machine.rs
@@ -64,9 +64,9 @@ impl Word {
         } else {
             l_clamp = l_clamp - 1;
         }
         } else {
             l_clamp = l_clamp - 1;
         }

-        let r_clamp = (fs.r - 1) % 5;
+        let r_clamp = fs.r % 6;

         let mut bytes = [MixBit::default(); 5];
         let mut bytes = [MixBit::default(); 5];

-        for n in l_clamp..=r_clamp {
+        for n in l_clamp..r_clamp {

             bytes[n] = self.bytes[n];
         }
         Word { sign, bytes }
             bytes[n] = self.bytes[n];
         }
         Word { sign, bytes }

diff --git a/src/main.rs b/src/main.rs
index 345f81eed470b7d37eea121ff18416cfe42261f5..24c2c6123f9869930d0e55eb93752aa52abb007d 100644 (file)
--- a/src/main.rs
+++ b/src/main.rs
@@ -21,7 +21,7 @@ fn main() {
             MixBit { v: 0 },
             MixBit { v: 0 },
             MixBit { v: 0 },
             MixBit { v: 0 },
             MixBit { v: 0 },
             MixBit { v: 0 },

-            MixBit { v: 29 },
+            MixBit { v: 5 },

             MixBit { v: 8 },
         ],
     };
             MixBit { v: 8 },
         ],
     };